The Next 15 Years of Moore’s Law: Imec’s Roadmap to CFETs and Beyond

San Francisco, USA — May 20, 2026 — The semiconductor industry’s relentless march toward smaller, faster, and more efficient chips has entered a new phase, according to Imec, the world’s leading research hub for nanoelectronics. At its annual technology forum, the Belgium-based organization unveiled its latest roadmap, projecting that the next major leap in transistor technology—the complementary field-effect transistor (CFET)—will begin commercial production around 2033. Beyond that, by 2041, chipmakers may transition to two-dimensional (2D) semiconductors to further slash power consumption. These predictions, while ambitious, reflect Imec’s role as a de facto bellwether for the industry’s long-term trajectory.

For decades, Moore’s Law has been sustained by successive generations of transistors—from planar to FinFET to nanosheet designs—each delivering exponential gains in performance per unit area. But as physical limits near, Imec’s roadmap signals a shift toward vertical integration and material innovation. The CFET, which stacks two transistors (PMOS and NMOS) in a single structure, could halve the footprint of certain circuits, while 2D semiconductors like molybdenum disulfide promise to reduce power consumption by enabling thinner transistor channels.

Yet the path to these breakthroughs is fraught with technical hurdles. Chip giants Intel, Samsung, and TSMC are already racing to perfect CFET prototypes, but fundamental challenges—like electrically isolating stacked transistors and optimizing manufacturing yields—remain unresolved. Meanwhile, the industry’s pivot toward 3D chip design (often called CMOS 2.0) could accelerate adoption of these new architectures, as vertical interconnects become denser and more reliable.

Why CFETs Are the Next Big Thing

Today’s chips rely on complementary metal-oxide-semiconductor (CMOS) logic, which pairs two types of transistors: PMOS (p-channel) and NMOS (n-channel). These transistors are traditionally built side by side, but CFETs propose stacking them vertically. The result? A ~50% reduction in area for certain logic circuits, according to Imec’s modeling.

The most promising CFET fabrication method involves depositing alternating layers of silicon and silicon-germanium on a wafer, then etching away the silicon-germanium to leave suspended nanosheets. The top nanosheets form the PMOS transistor, while the bottom become NMOS. This approach avoids the complexity of bonding separate wafers, though it introduces new challenges in electrical isolation and performance balancing.

Paul Heremans, Imec’s chief technology officer, emphasized that the roadmap’s 15-year horizon reflects the organization’s mission to de-risk technologies for chipmakers. “Our research programs explore the costs and benefits of different options to narrow the field for industry,” Heremans stated. “By the time these technologies reach production, there will still be years of engineering work ahead.”

“We have to be well ahead of the introduction timeline because after our de-risking work, there’s still a lot of development needed to get these into real products.”

CFET Prototypes: Who’s Leading the Race?

All three major foundries—Intel, Samsung, and TSMC—are actively developing CFETs, each with distinct approaches:

• TSMC: Demonstrated a compact memory cell and ring oscillator using CFETs at the IEEE International Electron Devices Meeting (IEDM) in December 2025.
• Samsung: Will unveil a CFET with six nanosheet layers at the IEEE VLSI Symposium in June 2026, claiming the smallest and most layered design to date.
• Intel: Is testing a wafer-bonding technique to improve PMOS/NMOS isolation, with results expected at the same June conference.

Despite these advancements, Heremans acknowledged that no single CFET design has emerged as the industry standard. “There are many versions still open,” he noted, highlighting ongoing debates over manufacturing complexity, yield, and performance trade-offs.

Beyond CFETs: The 2041 Shift to 2D Semiconductors

While CFETs focus on squeezing more transistors into the same space, the next major leap—projected for 2041—will prioritize power efficiency. Imec anticipates replacing silicon channels in CFETs with 2D semiconductors, which are less than a nanometer thick. These materials, such as molybdenum disulfide (MoS₂), could enable transistors that switch at lower voltages, drastically reducing energy consumption.

Heremans explained that 2D semiconductors could also improve charge mobility, further boosting performance per watt. “The goal is to increase operations per watt,” he said. “Even a small voltage reduction in advanced chips has a massive impact on power.”

3D Integration: The Backbone of CMOS 2.0

CFETs and 2D semiconductors won’t arrive in a vacuum. By 2033, the industry will have over a decade of experience with 3D chip stacking, as seen in AMD’s MI300 GPU, where compute tiles are stacked atop memory dies. Imec’s roadmap suggests this trend will accelerate, with wafer-to-wafer bonding technologies now capable of 200nm pitch interconnects—meaning 25 million connections per square millimeter.

This density enables CMOS 2.0, where chips are built by fusing layers optimized for specific functions (e.g., memory, logic, or power delivery). “Designers can now create logic circuits in 3D dies,” Heremans said. “This gives an enormous boost to what You can expect from fused chips.”

EUV Lithography: The Enabler of Smaller Nodes

Extreme ultraviolet (EUV) lithography will remain critical through the 2030s, with Imec projecting the adoption of 0.55NA EUV tools—a high-numerical-aperture variant that can print finer features than today’s 0.33NA machines. These tools will be essential for manufacturing CFETs and beyond, as they allow for sub-7nm patterning.

What’s Next? Key Milestones to Watch

The semiconductor industry’s roadmap is dynamic, but several confirmed checkpoints will shape the next decade:

• June 2026: Samsung and Intel will present CFET advancements at the IEEE VLSI Symposium, including Intel’s wafer-bonding results.
• 2028–2030: First commercial CFET test chips expected from foundries, with volume production targeting 2033.
• 2035–2040: Industry-wide adoption of 3D chip stacking and hybrid bonding for CMOS 2.0 designs.
• 2041: Potential transition to 2D semiconductor channels in advanced nodes.

Why This Matters for Consumers and Industries

The implications of Imec’s roadmap extend far beyond semiconductor labs. For consumers, CFETs and 2D materials could enable:

• Longer battery life in smartphones and laptops due to lower power consumption.
• More compact AI accelerators, as CFETs reduce the area needed for neural network chips.
• Advanced automotive chips, where power efficiency is critical for electric vehicles.

For industries, the shift to 3D integration and new materials could unlock:

• Data center efficiency, reducing the cooling costs of massive server farms.
• Edge computing breakthroughs, enabling smarter IoT devices with on-chip AI.
• Quantum computing co-processors, as 2D materials may offer advantages for qubit control.

Final Thoughts: A Roadmap with Caution

Imec’s projections are ambitious, but the semiconductor industry has a history of delivering on long-term promises—often with unexpected twists. While CFETs and 2D semiconductors are on track, unforeseen challenges (e.g., manufacturing bottlenecks, material defects, or economic shifts) could alter timelines. What’s certain is that the next 15 years will redefine what’s possible in computing, driven by innovations that push the boundaries of physics and engineering.

For now, chipmakers, researchers, and investors should keep an eye on:

• Progress at the IEEE VLSI Symposium 2026 (June).
• Imec’s annual roadmap updates, particularly for CMOS 2.0 and 2D materials.
• Foundry announcements on CFET manufacturing readiness.

As Heremans put it: “The semiconductor industry thrives on innovation, and these roadmaps are our best guess at what’s next. But the real magic happens when engineers turn those guesses into reality.”

What do you think? Will CFETs and 2D semiconductors live up to the hype? Share your predictions in the comments below, and don’t forget to follow World Today Journal for updates on the latest in tech and innovation.