Major semiconductor manufacturers are diverging on the technical architecture for future transistor stacking, a move essential for shrinking next-generation logic circuits. While industry leaders agree that future designs will utilize complementary field-effect transistors (CFETs)—stacking p-channel and n-channel devices vertically—research presented at the IEEE VLSI Symposium in Honolulu indicates a split in how companies like Intel, Samsung, TSMC, and IBM intend to achieve this integration.
The transition to CFET architecture represents a significant shift from current side-by-side CMOS logic, aiming to pack more devices into the same silicon footprint. According to research details, commercial adoption of these stacked devices is expected to be roughly six years away. As chipmakers look toward this horizon, the industry remains divided between “monolithic” and “sequential” manufacturing processes, each presenting unique thermal and structural challenges.
The Monolithic Approach: Intel, Samsung, and TSMC
The majority of the semiconductor industry appears to be converging on the monolithic process for CFET construction. In this scheme, both the top and bottom transistors are fabricated simultaneously in a single vertical stack. According to Myunghee Na, a CFET expert and vice president at Intel, the monolithic approach is widely viewed as the leading integration scheme across the industry.
Implementing this architecture requires stacking nanosheets, a gate-all-around technology recently introduced to mass production. The complexity arises in managing the connections and spacing within this confined vertical area. Intel, for example, is navigating a design compromise; while adding more nanosheets can increase switching speed, it also introduces signal-sapping capacitance that can degrade power efficiency. Jami Wiedemer, a device engineer at Intel, noted at the IEEE VLSI Symposium that current two-by-two structures are likely to evolve as the technology reaches maturity.
Foundries are also experimenting with electrical modifications to optimize these stacks. TSMC has reported success in creating CFETs where threshold voltages—the voltage required to switch a transistor on or off—can be set to three different levels for both the top and bottom devices. Meanwhile, Intel is utilizing different crystal orientations for the top and bottom silicon layers to optimize performance for PFETs and NFETs, respectively, by bonding separate wafers. Samsung has adopted a distinct method involving the growth of additional “sacrificial” nanosheets between the active devices, which are subsequently etched away and replaced with insulating dielectric material.
Sequential Integration: The IBM Path
IBM has diverged from the monolithic consensus by prioritizing a sequential integration process. In this method, the manufacturer completes the bottom layer of transistors entirely before building the second layer on top. This approach, which IBM markets as “Nanostack,” is intended to offer significant density and performance advantages. According to Huiming Bu, IBM Semiconductors vice president of global R&D, the technology is intended as a new platform rather than a singular innovation, with projections suggesting up to a 50 percent boost in performance and a 70 percent improvement in efficiency compared to current 2-nanometer-node chips.
The primary hurdle for the sequential approach has traditionally been the extreme heat involved in the manufacturing process. “The key trade-off is that the lower FET tiers must withstand the full thermal budget of the tiers above it,” Nirmaan Shanker, a research scientist at IBM Research, explained at the symposium. These temperatures can exceed 900 °C for several hours, potentially impacting current delivery and switching stability. IBM researchers have demonstrated methods to ensure both NFETs and PFETs can survive these thermal conditions, suggesting that the process could theoretically support more than two tiers of transistors in the future.
Furthermore, IBM is pursuing a “staggered” layout for its stacked transistors. By offsetting the top and bottom tiers rather than stacking them in perfect alignment, the company claims it can simplify the complex task of routing power and data signals. This staggered configuration is a key factor in the company’s projection of a 40 percent reduction in memory circuit size.
Connectivity Challenges and Future Outlook
Regardless of the fabrication method, managing electrical connectivity remains a primary constraint. Because CFETs are so dense, routing power from the bottom and data signals from the top requires precise engineering to avoid the “shadow” of other components. TSMC is currently exploring vertical connections alongside the source and drain, while Intel uses an “intraconnect” formed within the transistor stack itself. Samsung’s approach involves cleaving through the source of the top transistor to link both devices to upper metal lines.
The industry is still in the research and development phase, with no final standard yet established. As the six-year window for commercial introduction nears, collaboration with semiconductor manufacturing equipment makers and electronic design-automation-software vendors will be critical. Further updates on these processes are expected at future industry conferences as the technology matures toward mass production.
Worth a look