The semiconductor industry has long faced a fundamental challenge: as transistors shrink, their performance degrades due to quantum mechanical effects and increased leakage current. One promising solution is 3D chip stacking, which allows manufacturers to build layers of transistors vertically rather than spreading them out horizontally. However, existing methods—like those used in AMD’s MI300 series—rely on through-silicon vias (TSVs) that create alignment and connectivity challenges, limiting how many layers can be effectively stacked.

Monolithic 3D chips, where layers are fabricated directly on top of each other, offer a more promising approach. They enable nanometer-scale precision in layer alignment and orders of magnitude denser connectivity than today’s 3D chips. But a major hurdle has been the need to fabricate upper layers at temperatures below 400°C to preserve underlying wiring—a constraint that has forced researchers to experiment with exotic materials like carbon nanotubes or 2D semiconductors, which often underperform compared to traditional silicon metal-oxide-semiconductor field-effect transistors (MOSFETs).

Now, a team led by Qing Cao, an associate professor of materials science and engineering at the University of Illinois Urbana-Champaign, has demonstrated that silicon can achieve monolithic 3D integration at temperatures as low as 200°C. Their secret? Junctionless transistors, a transistor design first proposed in 1925 but only recently made practical with advances in nanofabrication. Unlike traditional MOSFETs, which rely on precise p-n junctions to control current flow, junctionless transistors use uniformly doped silicon channels that eliminate these junctions entirely. This simplification reduces fabrication complexity and cost while enabling low-temperature processing.

The Junctionless Advantage

Traditional MOSFETs require high temperatures (often over 1,000°C) to precisely dope silicon and create the p-n junctions that control current flow. These junctions act as barriers, allowing current to pass only when a gate voltage is applied. In contrast, junctionless transistors use a single type of doping—either n-type (electron-rich) or p-type (hole-rich)—throughout the source, channel and drain. When a gate voltage is applied, the entire channel becomes conductive, allowing current to flow without the need for high-temperature processing.

“For years, people assumed monolithic 3D would require exotic new materials such as carbon nanotubes, metal-oxide semiconductors, or 2D semiconductors. Demonstrating that silicon can do the job means this technology can plug directly into existing manufacturing ecosystems, which dramatically accelerates its path toward real impact.”

The team’s breakthrough lies in their ability to fabricate uniformly doped single-crystal silicon membranes just 10 nanometers thick using a wafer-scale roll-transfer-printing process. These membranes are thin and flexible enough to conform to underlying surfaces, avoiding the voids and warpage that plague traditional wafer bonding methods. The process also eliminates the need for ultra-smooth surfaces (sub-1-nanometer roughness), which current industry methods require for successful bonding.

How the Technology Works

The fabrication process begins with the creation of single-crystal silicon membranes doped uniformly with either boron (for p-type) or phosphorus (for n-type). These membranes are then transferred onto a base wafer using a roll-lamination technique that applies uniform pressure across the entire surface. The team employed several engineering innovations to ensure defect-free transfers, including:

• Surfactants during etching to reduce surface tension and prevent wrinkling.
• Polymer support layers for mechanical stability and surface protection.
• Roll-lamination to apply even pressure during membrane transfer.

In their demonstration, the researchers fabricated three layers of junctionless transistors on a 75-millimeter silicon wafer. Each layer contained 625 transistors across a 1,600-square-millimeter area, forming a variety of logic circuits including:

• Inverters
• NAND and NOR gates
• Static random access memory (SRAM) cells

The vertical connections between layers were aligned with sub-10-nanometer accuracy, enabling the creation of a six-transistor SRAM cell with a footprint just one-third the size of its 2D equivalent. This dramatic reduction in area could lead to significant improvements in chip density and performance.

Performance and Potential Applications

One of the most critical metrics for transistor performance is current density, which determines switching speed. The junctionless transistors demonstrated current densities exceeding 650 milliamperes per micrometer, comparable to older commercial silicon MOSFETs. While more advanced MOSFETs can achieve current densities over 1,000 mA/μm, the researchers note that their technology has room for improvement through further engineering optimizations.

The implications of this breakthrough are far-reaching. Saptarshi Das, a professor of engineering science and mechanics at Pennsylvania State University, highlights the potential impact:

“The key implication is that vertical stacking may not have to come with a severe transistor-performance penalty. If scalable, this could open a practical path to denser, more energy-efficient chips with much shorter interconnects.”

Beyond traditional computing, the technology could enable entirely new applications by integrating silicon with other materials in monolithic 3D devices. For example, vertically stacking different types of single-crystalline semiconductors could lead to:

• Ultrasensitive X-ray detector panels for medical imaging and security screening.
• Compact multispectral imaging systems for environmental monitoring and satellite applications.
• Advanced neuromorphic computing that mimics the brain’s structure for AI and machine learning.

Challenges and the Path Forward

Despite the promising results, several challenges remain before this technology can be commercialized at scale. The researchers acknowledge two primary hurdles:

The research team began their work in 2019 and achieved a major milestone in 2024 when they solved the fundamental barriers to low-temperature silicon stacking. The following 18 months were spent refining the process and demonstrating multilayered devices at wafer scale. Now, they are seeking partnerships with semiconductor foundries to validate the technology in a manufacturing environment.

Cao emphasizes a pragmatic approach to commercialization:

“Once the benefits of monolithic 3D integration are clearly established, People can work toward high-volume manufacturing. We simply want to be realistic and avoid over-claiming before the technology has been validated in those settings with full cost analysis.”

The team’s ultimate goal is to integrate this technology into existing semiconductor manufacturing ecosystems. Because their approach is silicon-based and compatible with current foundry processes, it has a realistic path to adoption—particularly for AI workloads, which are increasingly limited by communication bottlenecks between processing layers. By bringing compute layers physically closer together, this technology could significantly reduce latency and improve energy efficiency in AI systems.

Expert Perspectives on the Breakthrough

The potential of this research has drawn attention from experts across the semiconductor industry. Veeresh Deshpande, an associate professor of electrical engineering at the Indian Institute of Technology Bombay, who was not involved in the study, highlights the significance of the roll-transfer process:

“The proposed method simplifies the process complexity and allows stacking several tiers of transistors, both for advanced computing and memory like DRAM. That the nano-membranes can transfer onto surfaces that are not necessarily perfectly flat is important because the current method typically used in industry requires sub-1-nanometer roughness for the surfaces to be bonded together and extremely flat—only a few microns of variations across the wafer.”

Deshpande’s comments underscore how this technology could overcome a major limitation in current 3D chip fabrication: the requirement for ultra-smooth surfaces. By enabling stacking on less perfectly flat substrates, the roll-transfer process opens the door to more flexible and scalable manufacturing approaches.

Why This Matters for the Semiconductor Industry

The semiconductor industry has been grappling with Moore’s Law slowdown for over a decade. While traditional 2D scaling has continued, the physical limits of silicon transistors are becoming increasingly apparent. 3D chip stacking represents one of the most promising paths to continue performance improvements without relying on ever-smaller feature sizes.

Current 3D chips, like those from AMD and Intel, use through-silicon vias (TSVs) to connect prefabricated layers. However, these TSVs create significant challenges:

• Alignment difficulties: Connecting layers requires precise alignment, limiting the number of viable connections.
• Performance trade-offs: The physical separation between layers increases signal delay and power consumption.
• Complex fabrication: The process requires multiple steps and high temperatures, increasing costs and complexity.

Monolithic 3D chips, by contrast, fabricate all layers directly on top of each other, enabling:

• Nanometer-scale precision: Layers can be aligned with sub-10 nm accuracy.
• Denser connectivity: Vertical connections reduce signal delays and improve power efficiency.
• Simpler manufacturing: Fewer steps and lower temperatures reduce costs and improve yield.

The junctionless transistor approach combines the benefits of monolithic 3D with the familiarity and reliability of silicon, making it an attractive solution for both high-performance computing and emerging applications like AI and neuromorphic systems.

The Future of 3D Chips

While the technology is still in its early stages, the potential applications are vast. The researchers envision several key areas where this breakthrough could have immediate impact:

The team’s findings were published in Nature on May 28, 2026, marking a significant milestone in semiconductor research. As they move forward, their focus will be on demonstrating the technology in a foundry environment and addressing the remaining challenges of yield and thermal management.

For now, the researchers are cautious about overstating the technology’s immediate impact. Cao notes that the approach is initially promising for research and low-volume prototyping applications. However, once the benefits of monolithic 3D integration are clearly established, the path to high-volume manufacturing could become much clearer.

Comparison: 2D chip layout (left) versus 3D stacked chip (right) with reduced footprint (Credit: Research team)