The relentless pursuit of more powerful artificial intelligence is bumping up against a fundamental bottleneck: the speed and energy demands of data access. As AI models grow increasingly complex, the traditional architecture of separating processing and memory is proving inadequate. A potential solution lies in a new generation of memory technology, and researchers at the University of California, San Diego (UCSD) have recently demonstrated a significant breakthrough in this area with a novel approach to Resistive RAM (RRAM). This innovation, unveiled at December’s IEEE International Electron Devices Meeting (IEDM), promises to bring computation closer to the data itself, potentially overcoming the limitations of the “memory wall” that currently constrains AI performance.
The core challenge is that even the fastest models are hampered by the time and energy required to shuttle data between the processor and memory. RRAM, a type of nonvolatile memory, offers a potential workaround by enabling computation *within* the memory itself. However, traditional RRAM designs have faced hurdles related to instability and difficulty in integration with standard processing technologies. The UCSD team, led by electrical engineer Duygu Kuzum, has tackled these challenges head-on by fundamentally redesigning how RRAM switches, creating what they call “bulk RRAM.” This new architecture could pave the way for more efficient and powerful AI systems, particularly in edge computing applications where energy efficiency is paramount.
Rethinking Resistive RAM: The Rise of Bulk RRAM
RRAM works by storing data as varying levels of resistance to the flow of electrical current. In a neural network, a key operation is the multiplication of large arrays of numbers followed by summation. Traditional RRAM aims to perform this analog computation by running current through an array of memory cells, effectively using the resistance levels to perform the calculations directly within the memory. However, conventional RRAM relies on creating low-resistance pathways, or “filaments,” within a higher-resistance material. Forming these filaments often requires high voltages, making integration with complementary metal-oxide-semiconductor (CMOS) technology – the foundation of modern processors – difficult. The filament formation process is often noisy and unpredictable, leading to data instability.
“We actually redesigned RRAM, completely rethinking the way it switches,” explained Kuzum in a UCSD news release. The UCSD team’s innovation lies in dispensing with filaments altogether. Instead, their bulk RRAM switches an entire layer from high to low resistance, eliminating the necessitate for high voltages and simplifying the device structure. This approach also avoids the need for a “selector transistor,” a component typically required in filament-based RRAM to isolate cells, which complicates 3D stacking and increases energy consumption. According to the IEEE Spectrum article, this breakthrough addresses key limitations of previous RRAM designs.
Shrinking and Stacking: Nanoscale Devices and 3D Integration
While others have explored bulk RRAM, the UCSD researchers have achieved significant advancements in both shrinking the devices and creating three-dimensional circuits. They successfully scaled the RRAM down to just 40 nanometers across and managed to stack as many as eight layers of bulk RRAM. This stacking capability is crucial for increasing memory density and performance. Each cell within the eight-layer stack can now represent 64 different resistance values, a substantial improvement over traditional filamentary RRAM, which is limited to fewer states. The UCSD stack exhibits resistance in the megaohm range, which Kuzum believes is optimal for parallel matrix operations – the computational backbone of many AI algorithms.
“One can actually tune it to anywhere we want, but we think that from an integration and system-level simulations perspective, megaohm is the desirable range,” Kuzum stated. This higher resistance, combined with the increased number of resistance levels, allows the bulk RRAM stack to perform more complex computations than previously possible. The team assembled multiple eight-layer stacks into a 1-kilobyte array without the need for selectors, demonstrating the feasibility of large-scale integration.
Demonstrating AI Capabilities: Continual Learning on the Edge
To validate their design, the researchers tested the 1-kilobyte array with a continual learning algorithm. This algorithm allowed the chip to classify data from wearable sensors – such as those found in smartphones – while continuously learning from new information. For example, the chip could distinguish between a person sitting, walking, or climbing stairs based on data collected from a waist-mounted smartphone. The tests yielded an accuracy of 90 percent, comparable to the performance of a digitally implemented neural network. This result highlights the potential of bulk RRAM for edge computing applications, where AI models need to learn and adapt in real-time without relying on cloud connectivity.
Kuzum envisions bulk RRAM being particularly beneficial for neural network models deployed on edge devices. These devices, operating closer to the data source, can benefit from the reduced latency and energy consumption offered by in-memory computing. “We are doing a lot of characterization and material optimization to design a device specifically engineered for AI applications,” Kuzum added.
Expert Perspective and Remaining Challenges
The integration of RRAM into an array like this represents a significant step forward, according to Alec Talin, a materials scientist at Sandia National Laboratories who was not involved in the UCSD research. “I think that any step in terms of integration is very useful,” Talin said. However, he also cautioned about a potential obstacle: data retention. While the UCSD team demonstrated that their RRAM could retain data for several years at room temperature – comparable to flash memory – its retention at the higher temperatures encountered during computer operation remains uncertain. “That’s one of the major challenges of this technology,” Talin explained, particularly for edge applications where devices may operate in challenging thermal environments.
The “memory wall” has become increasingly problematic as traditional memory technologies struggle to keep pace with the growing demands of large AI models. Any technology that allows computation to occur directly within the memory itself offers a promising shortcut. The IEEE International Electron Devices Meeting (IEDM), held annually, serves as a crucial forum for showcasing these advancements. The 71st annual IEDM was held December 6-10, 2025, in San Francisco, and the 72nd is scheduled for December 12-16, 2026, also in San Francisco, according to the IEDM website. The conference has a long history of fostering innovation in micro- and nanoelectronics, notably being the venue where Gordon Moore first refined his predictions about the exponential growth of integrated circuits – now known as Moore’s Law – in 1965, as detailed on Wikipedia.
Key Takeaways
- Bulk RRAM offers a potential solution to the AI “memory wall” by enabling computation within the memory itself.
- The UCSD team’s innovation lies in eliminating filaments, simplifying the device structure and improving integration with CMOS technology.
- 3D stacking of bulk RRAM increases memory density and performance, with the team achieving eight layers in their prototype.
- The technology demonstrated 90% accuracy in a continual learning task, highlighting its potential for edge computing applications.
- Data retention at higher temperatures remains a key challenge for widespread adoption.
The future of AI hinges on overcoming the limitations of current memory technology. While challenges remain, the advancements demonstrated by the UCSD team represent a significant step towards a new era of more efficient and powerful AI systems. Further research and development will be crucial to address the data retention concerns and fully unlock the potential of bulk RRAM. The next major update on this research is anticipated at the 2026 IEEE IEDM conference in December. Share your thoughts on the future of AI and memory technology in the comments below.
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