Researchers have reached new milestones in 3D chipmaking technology, significantly increasing the density of electrical connections within stacked semiconductor devices. By refining hybrid bonding processes, two separate teams—one led by the Belgium-based research center Imec and the other by the French laboratory CEA-Leti—achieved record-breaking bond pitches at the IEEE Electronic Components and Technology Conference (ECTC) in Orlando, Florida. These advancements allow for more efficient, high-performance computing by stacking chips in a three-dimensional configuration, effectively bypassing the physical size limitations of traditional 2D transistor scaling.
As transistor dimensions approach atomic limits, the semiconductor industry is increasingly relying on 3D integration to maintain performance gains. Hybrid bonding serves as a critical enabler for this transition, using heat and pressure to join copper pads on the surfaces of stacked chips. A smaller bond pitch—the distance between these copper connections—directly translates to a higher number of interconnects per square millimeter, which improves communication speed and reduces power consumption for high-performance computing, artificial intelligence, and high-bandwidth memory applications.
Wafer-to-Wafer Innovation at Imec
Imec, in collaboration with equipment manufacturer EV Group, set a new record for wafer-to-wafer (W2W) hybrid bonding, successfully reducing the bond pitch to 200 nanometers. This figure represents a notable improvement over the 250-nanometer benchmark reported by the organization last year. According to Zsolt Tokei, Imec’s program director of 3D system integration, the team achieved this density by refining chemical mechanical polishing (CMP) techniques to ensure the connection surfaces were sufficiently flat, alongside enhancements to copper-pad design and wafer alignment accuracy.
The W2W approach is particularly well-suited for logic and memory applications where uniformity across the entire wafer is standard. However, the process remains technically demanding; alignment must be accurate to within approximately 50 nanometers. While other research institutes have reportedly achieved pitches below 200 nanometers, industry observers like Srinidhi Ramamoorthy, a heterogeneous integration engineer at Applied Materials, note that such figures often lack the accompanying electrical testing and reliability data required to qualify them as finalized industry standards.
Die-to-Wafer Advances at CEA-Leti
CEA-Leti achieved a record for die-to-wafer (D2W) hybrid bonding, reaching a 1-micrometer (μm) pitch. While this is larger than the W2W milestone, it marks a 50 percent reduction from the previous 2-μm record. The D2W method functions by placing individual chips, or “dies,” onto a full wafer, offering greater flexibility for manufacturers who need to mix and match chips of different sizes and functions. Melissa Najem, a research engineer at CEA-Leti, explained that the team reached this milestone by fine-tuning alignment processes and improving surface polishing.
The practical application of this technology involves rigorous testing to ensure electrical viability. In CEA-Leti’s recent trials, the team utilized a specialized test vehicle to evaluate connections at various pitch levels. While electrical yields remained high—approximately 90 percent—for pitches above 1 μm, the yield dropped to 22 percent at the 1-μm limit. Improving this yield remains a primary focus for future research, as understanding the efficiency of these interconnections is vital for scaling the technology into mass production.
Industry Context and Global Competition
The drive toward 3D stacking is also being influenced by global geopolitical factors. Following U.S. export controls that restricted access to certain advanced chipmaking tools, Huawei has increasingly focused on 3D stacking to maintain transistor density in its processors. Last month, at the IEEE International Symposium on Circuits and Systems in Shanghai, the company announced that it had implemented a 1.5-μm hybrid-bonding pitch in its upcoming Kirin processor generation. While the specific methods used by Huawei remain unconfirmed, industry experts emphasize that multiple technical pathways exist to achieve these results.
Despite the rapid progress in lab environments, moving these records into commercial manufacturing remains a hurdle. Gabriela Pereira, a senior semiconductor packaging technology and market analyst at Yole Group, notes that current mass production pitches generally sit between 6–9 μm for D2W and 1–2 μm for W2W. The transition from research to high-volume manufacturing requires significant improvements in speed, reliability, and replicability. Given the flexibility offered by die-to-wafer methods, industry analysts suggest that manufacturers may eventually prioritize D2W technology as the primary vehicle for future 3D integration.
The next major checkpoint for these technologies will be the further publication of reliability data and the refinement of high-yield manufacturing processes, which are essential for commercial deployment. Updates regarding these developments are expected to follow in future industry forums and technical conferences as research teams continue to push the boundaries of semiconductor packaging.